{
   "arrays" : [
      {
         "name" : "MemRef_tmp4",
         "sizes" : [ "*" ],
         "type" : "i32"
      },
      {
         "name" : "MemRef__pn",
         "sizes" : [ "*" ],
         "type" : "i32"
      }
   ],
   "context" : "[tmp5] -> {  : -2147483648 <= tmp5 <= 2147483647 }",
   "name" : "%for.body344---%if.then.i.i1141.loopexit",
   "statements" : [
      {
         "accesses" : [
            {
               "kind" : "write",
               "relation" : "[tmp5] -> { Stmt_for_body344[-1 + tmp5] -> MemRef__pn[-1 + tmp5] }"
            }
         ],
         "domain" : "[tmp5] -> { Stmt_for_body344[i0] : 0 <= i0 < tmp5; Stmt_for_body344[0] : tmp5 <= 0 }",
         "name" : "Stmt_for_body344",
         "schedule" : "[tmp5] -> { Stmt_for_body344[i0] -> [i0, 0] : i0 < tmp5; Stmt_for_body344[0] -> [0, 0] : tmp5 <= 0 }"
      },
      {
         "accesses" : [
            {
               "kind" : "read",
               "relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef_tmp4[1 + i0] }"
            },
            {
               "kind" : "write",
               "relation" : "[tmp5] -> { Stmt_cond_false[i0] -> MemRef__pn[i0] : i0 <= -2 + tmp5; Stmt_cond_false[0] -> MemRef__pn[0] : tmp5 <= 0 }"
            }
         ],
         "domain" : "[tmp5] -> { Stmt_cond_false[i0] : 0 <= i0 <= -2 + tmp5; Stmt_cond_false[0] : tmp5 <= 0 }",
         "name" : "Stmt_cond_false",
         "schedule" : "[tmp5] -> { Stmt_cond_false[i0] -> [i0, 1] : i0 <= -2 + tmp5; Stmt_cond_false[0] -> [0, 1] : tmp5 <= 0 }"
      },
      {
         "accesses" : [
            {
               "kind" : "read",
               "relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
            },
            {
               "kind" : "write",
               "relation" : "[tmp5] -> { Stmt_cond_end[i0] -> MemRef__pn[i0] }"
            }
         ],
         "domain" : "[tmp5] -> { Stmt_cond_end[i0] : 0 <= i0 < tmp5; Stmt_cond_end[0] : tmp5 <= 0 }",
         "name" : "Stmt_cond_end",
         "schedule" : "[tmp5] -> { Stmt_cond_end[i0] -> [i0, 2] : i0 < tmp5; Stmt_cond_end[0] -> [0, 2] : tmp5 <= 0 }"
      }
   ]
}
