/* Generated automatically by the program `genoutput'
   from the machine description file `md'.  */

#include "config.h"
#include "system.h"
#include "flags.h"
#include "ggc.h"
#include "rtl.h"
#include "expr.h"
#include "insn-codes.h"
#include "tm_p.h"
#include "function.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "real.h"
#include "insn-config.h"

#include "conditions.h"
#include "insn-attr.h"

#include "recog.h"

#include "toplev.h"
#include "output.h"

static const char * const output_2[] = {
  "sub.b	%X0,%X0",
  "mov.b	%R1,%X0",
  "mov.b	%X1,%R0",
  "mov.b	%R1,%X0",
  "mov.b	%R1,%X0",
  "mov.b	%X1,%R0",
};

static const char * const output_3[] = {
  "sub.b	%X0,%X0",
  "mov.b	%R1,%X0",
  "mov.b	%X1,%R0",
  "mov.b	%R1,%X0",
  "mov.b	%R1,%X0",
  "mov.b	%X1,%R0",
};

static const char * const output_4[] = {
  "sub.b	%X0,%X0",
  "mov.b	%X1,%X0",
  "mov.b	%R1,%X0",
  "mov.b	%R1,%X0",
};

static const char * const output_6[] = {
  "sub.w	%T0,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
};

static const char * const output_7[] = {
  "sub.w	%T0,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
};

static const char * const output_8[] = {
  "sub.w	%T0,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
  "mov.w	%T1,%T0",
};

static const char *output_9 PARAMS ((rtx *, rtx));

static const char *
output_9 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  int rn = -1;
  switch (which_alternative)
    {
    case 0:
      return "sub.w	%e0,%e0\n\tsub.w	%f0,%f0";
    case 1:
      if (REGNO (operands[0]) < REGNO (operands[1]))
	return "mov.w	%e1,%e0\n\tmov.w	%f1,%f0";
      else
	return "mov.w	%f1,%f0\n\tmov.w	%e1,%e0";
    case 2:
      /* Make sure we don't trample the register we index with.  */
      if (GET_CODE (operands[1]) == MEM)
	{
	  rtx inside = XEXP (operands[1], 0);
	  if (REG_P (inside))
	    {
	      rn = REGNO (inside);
	    }
	  else if (GET_CODE (inside) == PLUS)
	    {
	      rtx lhs = XEXP (inside, 0);
	      rtx rhs = XEXP (inside, 1);
	      if (REG_P (lhs)) rn = REGNO (lhs);
	      if (REG_P (rhs)) rn = REGNO (rhs);
	    }
	}
      if (rn == REGNO (operands[0]))
	{
	  /* Move the second word first.  */
	  return "mov.w	%f1,%f0\n\tmov.w	%e1,%e0";
	}
      else
	{
	  /* See if either half is zero.  If so, use sub.w to clear
	     that half.  */
	  if (GET_CODE (operands[1]) == CONST_INT)
	    {
	      if ((INTVAL (operands[1]) & 0xffff) == 0)
		return "mov.w	%e1,%e0\n\tsub.w	%f0,%f0";
	      if (((INTVAL (operands[1]) >> 16) & 0xffff) == 0)
		return "sub.w	%e0,%e0\n\tmov.w	%f1,%f0";
	    }
	  return "mov.w	%e1,%e0\n\tmov.w	%f1,%f0";
	}
    case 3:
      return "mov.w	%e1,%e0\n\tmov.w	%f1,%f0";
    case 4:
      return "mov.w	%f1,%T0\n\tmov.w	%e1,%T0";
    case 5:
      return "mov.w	%T1,%e0\n\tmov.w	%T1,%f0";
    default:
      abort ();
    }
}
}

static const char *output_10 PARAMS ((rtx *, rtx));

static const char *
output_10 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  /* Copy of the movsi stuff.  */
  int rn = -1;
  switch (which_alternative)
    {
    case 0:
      return "sub.w	%e0,%e0\n\tsub.w	%f0,%f0";
    case 1:
      if (REGNO (operands[0]) < REGNO (operands[1]))
	return "mov.w	%e1,%e0\n\tmov.w	%f1,%f0";
      else
	return "mov.w	%f1,%f0\n\tmov.w	%e1,%e0";
    case 2:
      /* Make sure we don't trample the register we index with.  */
      if (GET_CODE (operands[1]) == MEM)
	{
	  rtx inside = XEXP (operands[1], 0);
	  if (REG_P (inside))
	    {
	      rn = REGNO (inside);
	    }
	  else if (GET_CODE (inside) == PLUS)
	    {
	      rtx lhs = XEXP (inside, 0);
	      rtx rhs = XEXP (inside, 1);
	      if (REG_P (lhs)) rn = REGNO (lhs);
	      if (REG_P (rhs)) rn = REGNO (rhs);
	    }
	}
      if (rn == REGNO (operands[0]))
	/* Move the second word first.  */
	return "mov.w	%f1,%f0\n\tmov.w	%e1,%e0";
      else
	/* Move the first word first.  */
	return "mov.w	%e1,%e0\n\tmov.w	%f1,%f0";

    case 3:
      return "mov.w	%e1,%e0\n\tmov.w	%f1,%f0";
    case 4:
      return "mov.w	%f1,%T0\n\tmov.w	%e1,%T0";
    case 5:
      return "mov.w	%T1,%e0\n\tmov.w	%T1,%f0";
    default:
      abort ();
    }
}
}

static const char *output_11 PARAMS ((rtx *, rtx));

static const char *
output_11 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  switch (which_alternative)
    {
    case 0:
      return "sub.l	%S0,%S0";
    case 7:
      return "clrmac";
    case 8:
      return "clrmac\n\tldmac %1,macl";
    case 9:
      return "stmac	macl,%0";
    default:
      if (GET_CODE (operands[1]) == CONST_INT)
	{
	  int val = INTVAL (operands[1]);

	  /* Look for constants which can be made by adding an 8-bit
	     number to zero in one of the two low bytes.  */
	  if (val == (val & 0xff))
	    {
	      operands[1] = GEN_INT ((char) val & 0xff);
	      return "sub.l\t%S0,%S0\n\tadd.b\t%1,%w0";
	    }

	  if (val == (val & 0xff00))
	    {
	      operands[1] = GEN_INT ((char) (val >> 8) & 0xff);
	      return "sub.l\t%S0,%S0\n\tadd.b\t%1,%x0";
	    }

	  /* Look for constants that can be obtained by subs, inc, and
             dec to 0.  */
	  switch (val & 0xffffffff)
	    {
	    case 0xffffffff:
	      return "sub.l\t%S0,%S0\n\tsubs\t#1,%S0";
	    case 0xfffffffe:
	      return "sub.l\t%S0,%S0\n\tsubs\t#2,%S0";
	    case 0xfffffffc:
	      return "sub.l\t%S0,%S0\n\tsubs\t#4,%S0";

	    case 0x0000ffff:
	      return "sub.l\t%S0,%S0\n\tdec.w\t#1,%f0";
	    case 0x0000fffe:
	      return "sub.l\t%S0,%S0\n\tdec.w\t#2,%f0";

	    case 0xffff0000:
	      return "sub.l\t%S0,%S0\n\tdec.w\t#1,%e0";
	    case 0xfffe0000:
	      return "sub.l\t%S0,%S0\n\tdec.w\t#2,%e0";

	    case 0x00010000:
	      return "sub.l\t%S0,%S0\n\tinc.w\t#1,%e0";
	    case 0x00020000:
	      return "sub.l\t%S0,%S0\n\tinc.w\t#2,%e0";
	    }
	}
    }
   return "mov.l	%S1,%S0";
}
}

static const char * const output_12[] = {
  "sub.l	%S0,%S0",
  "mov.l	%S1,%S0",
  "mov.l	%S1,%S0",
  "mov.l	%S1,%S0",
  "mov.l	%S1,%S0",
  "mov.l	%S1,%S0",
};

static const char * const output_25[] = {
  "adds	%2,%T0",
  "subs	%G2,%T0",
  "add.b	%s2,%s0\n\taddx	%t2,%t0",
  "add.w	%T2,%T0",
  "mov.w	%T1,%T0\n\tadd.w	%T2,%T0",
};

static const char * const output_26[] = {
  "adds	%2,%S0",
  "subs	%G2,%S0",
  "add.w	%T2,%T0",
  "add.w	%T2,%T0",
};

static const char * const output_27[] = {
  "add	%w2,%w0\n\taddx	%x2,%x0\n\taddx	%y2,%y0\n\taddx	%z2,%z0",
  "add.w	%f2,%f0\n\taddx	%y2,%y0\n\taddx	%z2,%z0",
  "mov.w	%f1,%f0\n\tmov.w	%e1,%e0\n\tadd.w	%f2,%f0\n\taddx	%y2,%y0\n\taddx	%z2,%z0",
};

static const char * const output_28[] = {
  "adds	%2,%S0",
  "subs	%G2,%S0",
  "add.l	%S2,%S0",
  "add.l	%S2,%S0",
};

static const char * const output_30[] = {
  "sub.w	%T2,%T0",
  "add.b	%E2,%s0\n\taddx	%F2,%t0",
};

static const char * const output_31[] = {
  "sub.w	%T2,%T0",
  "sub.w	%T2,%T0",
};

static const char * const output_33[] = {
  "sub.l	%S2,%S0",
  "sub.l	%S2,%S0",
};

static const char *output_40 PARAMS ((rtx *, rtx));

static const char *
output_40 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return "divxu.b\t%X2,%T0";
  else
    return "divxu.b\t%X2,%T0\n\tmov.b\t%t0,%s3";
}
}

static const char *output_41 PARAMS ((rtx *, rtx));

static const char *
output_41 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return "divxs.b\t%X2,%T0";
  else
    return "divxs.b\t%X2,%T0\n\tmov.b\t%t0,%s3";
}
}

static const char *output_42 PARAMS ((rtx *, rtx));

static const char *
output_42 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return "divxu.w\t%T2,%S0";
  else
    return "divxu.w\t%T2,%S0\n\tmov.w\t%e0,%f3";
}
}

static const char *output_43 PARAMS ((rtx *, rtx));

static const char *
output_43 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  if (find_reg_note (insn, REG_UNUSED, operands[3]))
    return "divxs.w\t%T2,%S0";
  else
    return "divxs.w\t%T2,%S0\n\tmov.w\t%e0,%f3";
}
}

static const char * const output_44[] = {
  "and	%X2,%X0",
  "bclr	%W2,%R0",
};

static const char *output_45 PARAMS ((rtx *, rtx));

static const char *
output_45 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  operands[3] = GEN_INT (INTVAL (operands[3]) & 0xffff);
  if (INTVAL (operands[3]) > 128)
    {
      operands[3] = GEN_INT (INTVAL (operands[3]) >> 8);
      return "bld\t%V3,%t2\n\tbst\t%V3,%t0";
    }
  return "bld\t%V3,%s2\n\tbst\t%V3,%s0";
}
}

static const char *output_46 PARAMS ((rtx *, rtx));

static const char *
output_46 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  switch (which_alternative)
    {
    case 0:
      return "or\t%X2,%X0";
    case 1:
      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
      return "bset\t%V2,%R0";
    default:
      abort ();
    }
}
}

static const char *output_47 PARAMS ((rtx *, rtx));

static const char *
output_47 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  switch (which_alternative)
    {
    case 0:
      return "xor\t%X2,%X0";
    case 1:
      operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
      return "bnot\t%V2,%R0";
    default:
      abort ();
    }
}
}

static const char *output_48 PARAMS ((rtx *, rtx));

static const char *
output_48 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return output_logical_op (HImode, operands);
}

static const char *output_49 PARAMS ((rtx *, rtx));

static const char *
output_49 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return output_logical_op (SImode, operands);
}

static const char *output_58 PARAMS ((rtx *, rtx));

static const char *
output_58 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
      && (GET_CODE (operands[1]) == GT
          || GET_CODE (operands[1]) == GE
          || GET_CODE (operands[1]) == LE
          || GET_CODE (operands[1]) == LT))
    {
      cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
      return 0;
    }

  if (get_attr_length (insn) == 2)
    return "b%j1	%l0";
  else if (get_attr_length (insn) == 4)
    return "b%j1	%l0:16";
  else
    return "b%k1	.Lh8BR%=\n\tjmp	@%l0\n.Lh8BR%=:";
}
}

static const char *output_59 PARAMS ((rtx *, rtx));

static const char *
output_59 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
      && (GET_CODE (operands[1]) == GT
          || GET_CODE (operands[1]) == GE
          || GET_CODE (operands[1]) == LE
          || GET_CODE (operands[1]) == LT))
    {
      cc_status.flags &= ~CC_OVERFLOW_UNUSABLE;
      return 0;
    }

  if (get_attr_length (insn) == 2)
    return "b%k1	%l0";
  else if (get_attr_length (insn) == 4)
    return "b%k1	%l0:16";
  else
    return "b%j1	.Lh8BR%=\n\tjmp	@%l0\n.Lh8BR%=:";
}
}

static const char *output_60 PARAMS ((rtx *, rtx));

static const char *
output_60 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  if (get_attr_length (insn) == 2)
    return "bra	%l0";
  else if (get_attr_length (insn) == 4)
    return "bra	%l0:16";
  else
    return "jmp	@%l0";
}
}

static const char *output_65 PARAMS ((rtx *, rtx));

static const char *
output_65 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
      && SYMBOL_REF_FLAG (XEXP (operands[0], 0)))
    return "jsr\t@%0:8";
  else
    return "jsr\t%0";
}
}

static const char *output_66 PARAMS ((rtx *, rtx));

static const char *
output_66 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{

{
  if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
      && SYMBOL_REF_FLAG (XEXP (operands[1], 0)))
    return "jsr\t@%1:8";
  else
    return "jsr\t%1";
}
}

static const char * const output_68[] = {
  "mov.b	#0,%t0",
  "mov.b	%R1,%s0\n\tmov.b	#0,%t0",
};

static const char * const output_69[] = {
  "extu.w	%T0",
  "mov.b	%R1,%s0\n\textu.w	%T0",
};

static const char * const output_70[] = {
  "mov.b	#0,%x0\n\tsub.w	%e0,%e0",
  "mov.b	%R1,%w0\n\tmov.b	#0,%x0\n\tsub.w	%e0,%e0",
};

static const char * const output_71[] = {
  "sub.w	%e0,%e0",
  "mov.w	%f1,%f0\n\tsub.w	%e0,%e0",
  "mov.w	%e1,%f0\n\tsub.w	%e0,%e0",
};

static const char * const output_73[] = {
  "bld	#7,%s0\n\tsubx	%t0,%t0",
  "mov.b	%R1,%s0\n\tbld	#7,%s0\n\tsubx	%t0,%t0",
};

static const char * const output_75[] = {
  "bld	#7,%w0\n\tsubx	%x0,%x0\n\tsubx	%y0,%y0\n\tsubx	%z0,%z0",
  "mov.b	%R1,%w0\n\tbld	#7,%w0\n\tsubx	%x0,%x0\n\tsubx	%y0,%y0\n\tsubx	%z0,%z0",
};

static const char * const output_76[] = {
  "bld	#7,%x0\n\tsubx	%y0,%y0\n\tsubx	%z0,%z0",
  "mov.w	%T1,%f0\n\tbld	#7,%x0\n\tsubx	%y0,%y0\n\tsubx	%z0,%z0",
};

static const char *output_78 PARAMS ((rtx *, rtx));

static const char *
output_78 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return output_a_shift (insn, operands);
}

static const char *output_79 PARAMS ((rtx *, rtx));

static const char *
output_79 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return output_a_shift (insn, operands);
}

static const char *output_80 PARAMS ((rtx *, rtx));

static const char *
output_80 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return output_a_shift (insn, operands);
}

static const char *output_81 PARAMS ((rtx *, rtx));

static const char *
output_81 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return emit_a_rotate (ROTATE, operands);
}

static const char *output_82 PARAMS ((rtx *, rtx));

static const char *
output_82 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return emit_a_rotate (ROTATE, operands);
}

static const char *output_83 PARAMS ((rtx *, rtx));

static const char *
output_83 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return emit_a_rotate (ROTATE, operands);
}

static const char *output_86 PARAMS ((rtx *, rtx));

static const char *
output_86 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return output_simode_bld (0, operands);
}

static const char *output_87 PARAMS ((rtx *, rtx));

static const char *
output_87 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return output_simode_bld (0, operands);
}

static const char *output_88 PARAMS ((rtx *, rtx));

static const char *
output_88 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return output_simode_bld (1, operands);
}

static const char *output_89 PARAMS ((rtx *, rtx));

static const char *
output_89 (operands, insn)
     rtx *operands ATTRIBUTE_UNUSED;
     rtx insn ATTRIBUTE_UNUSED;
{
 return output_simode_bld (1, operands);
}


extern int register_operand PARAMS ((rtx, enum machine_mode));
extern int general_operand_dst PARAMS ((rtx, enum machine_mode));
extern int general_operand_src PARAMS ((rtx, enum machine_mode));
extern int bit_memory_operand PARAMS ((rtx, enum machine_mode));
extern int const_int_operand PARAMS ((rtx, enum machine_mode));
extern int nonmemory_operand PARAMS ((rtx, enum machine_mode));
extern int general_operand PARAMS ((rtx, enum machine_mode));
extern int bit_operand PARAMS ((rtx, enum machine_mode));
extern int bit_operator PARAMS ((rtx, enum machine_mode));
extern int comparison_operator PARAMS ((rtx, enum machine_mode));
extern int jump_address_operand PARAMS ((rtx, enum machine_mode));
extern int call_insn_operand PARAMS ((rtx, enum machine_mode));
extern int nshift_operator PARAMS ((rtx, enum machine_mode));
extern int scratch_operand PARAMS ((rtx, enum machine_mode));
extern int immediate_operand PARAMS ((rtx, enum machine_mode));
extern int two_insn_adds_subs_operand PARAMS ((rtx, enum machine_mode));



static const struct insn_operand_data operand_data[] = 
{
  {
    0,
    "",
    VOIDmode,
    0,
    0
  },
  {
    register_operand,
    "r",
    QImode,
    0,
    1
  },
  {
    general_operand_dst,
    "=r,r,<,r,r,m",
    QImode,
    0,
    1
  },
  {
    general_operand_src,
    "I,r>,r,n,m,r",
    QImode,
    0,
    1
  },
  {
    general_operand_dst,
    "+r,r,r,r",
    QImode,
    1,
    1
  },
  {
    general_operand_src,
    "I,r,n,m",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    general_operand_dst,
    "=r,r,<,r,r,m",
    HImode,
    0,
    1
  },
  {
    general_operand_src,
    "I,r>,r,i,m,r",
    HImode,
    0,
    1
  },
  {
    general_operand_dst,
    "+r,r,r,r",
    HImode,
    1,
    1
  },
  {
    general_operand_src,
    "I,r,i,m",
    HImode,
    0,
    1
  },
  {
    general_operand_dst,
    "=r,r,r,o,<,r",
    SImode,
    0,
    1
  },
  {
    general_operand_src,
    "I,r,io,r,r,>",
    SImode,
    0,
    1
  },
  {
    general_operand_dst,
    "=r,r,r,o,<,r",
    SFmode,
    0,
    1
  },
  {
    general_operand_src,
    "I,r,io,r,r,>",
    SFmode,
    0,
    1
  },
  {
    general_operand_dst,
    "=r,r,r,r,m,<,r,*a,*a,r",
    SImode,
    0,
    1
  },
  {
    general_operand_src,
    "I,r,i,m,r,r,>,I,r,*a",
    SImode,
    0,
    1
  },
  {
    general_operand_dst,
    "=r,r,r,m,<,r",
    SFmode,
    0,
    1
  },
  {
    general_operand_src,
    "I,r,im,r,r,>",
    SFmode,
    0,
    1
  },
  {
    bit_memory_operand,
    "r,U",
    QImode,
    0,
    1
  },
  {
    const_int_operand,
    "n,n",
    VOIDmode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    VOIDmode,
    0,
    1
  },
  {
    register_operand,
    "r",
    SImode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    VOIDmode,
    0,
    1
  },
  {
    register_operand,
    "r",
    QImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "rn",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r,r",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "r,n",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r,r",
    SImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "r,i",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "%0",
    QImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "rn",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r,r,r,&r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "%0,0,0,0,g",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "L,N,n,r,r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r,r,r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "%0,0,0,0",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "L,N,n,r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r,&r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "%0,0,r",
    SImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "n,r,r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r,r,r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "%0,0,0,0",
    SImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "L,N,i,r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r,&r",
    HImode,
    0,
    1
  },
  {
    general_operand,
    "0,0",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "r,n",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r",
    SImode,
    0,
    1
  },
  {
    general_operand,
    "0,0",
    SImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "r,i",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "%0",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "%0",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=a",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    HImode,
    0,
    1
  },
  {
    bit_operand,
    "=r,U",
    QImode,
    0,
    1
  },
  {
    bit_operand,
    "%0,0",
    QImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "rn,O",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    HImode,
    0,
    1
  },
  {
    bit_operand,
    "=r,U",
    QImode,
    0,
    1
  },
  {
    bit_operand,
    "%0,0",
    QImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "rn,n",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "%0",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "rn",
    HImode,
    0,
    1
  },
  {
    bit_operator,
    "",
    HImode,
    0,
    0
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "%0",
    SImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "rn",
    SImode,
    0,
    1
  },
  {
    bit_operator,
    "",
    SImode,
    0,
    0
  },
  {
    0,
    "",
    VOIDmode,
    0,
    1
  },
  {
    comparison_operator,
    "",
    VOIDmode,
    0,
    0
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    0,
    "",
    VOIDmode,
    0,
    1
  },
  {
    register_operand,
    "r",
    SImode,
    0,
    1
  },
  {
    0,
    "",
    VOIDmode,
    0,
    1
  },
  {
    jump_address_operand,
    "Vr",
    HImode,
    0,
    1
  },
  {
    jump_address_operand,
    "Vr",
    SImode,
    0,
    1
  },
  {
    call_insn_operand,
    "or",
    QImode,
    0,
    1
  },
  {
    general_operand,
    "g",
    HImode,
    0,
    1
  },
  {
    0,
    "=r",
    VOIDmode,
    0,
    1
  },
  {
    call_insn_operand,
    "or",
    QImode,
    0,
    1
  },
  {
    general_operand,
    "g",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r",
    HImode,
    0,
    1
  },
  {
    general_operand_src,
    "0,g>",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r",
    SImode,
    0,
    1
  },
  {
    general_operand_src,
    "0,g>",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r,r",
    SImode,
    0,
    1
  },
  {
    general_operand_src,
    "0,i,g>",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r",
    SImode,
    0,
    1
  },
  {
    general_operand_src,
    "0,g>",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r,r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "0,0",
    QImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "KM,rn",
    QImode,
    0,
    1
  },
  {
    nshift_operator,
    "",
    QImode,
    0,
    0
  },
  {
    scratch_operand,
    "=X,&r",
    QImode,
    0,
    0
  },
  {
    register_operand,
    "=r,r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "0,0",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "KM,rn",
    QImode,
    0,
    1
  },
  {
    nshift_operator,
    "",
    HImode,
    0,
    0
  },
  {
    scratch_operand,
    "=X,&r",
    QImode,
    0,
    0
  },
  {
    register_operand,
    "=r,r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "0,0",
    SImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "K,rn",
    QImode,
    0,
    1
  },
  {
    nshift_operator,
    "",
    SImode,
    0,
    0
  },
  {
    scratch_operand,
    "=X,&r",
    QImode,
    0,
    0
  },
  {
    register_operand,
    "=r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    QImode,
    0,
    1
  },
  {
    immediate_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    HImode,
    0,
    1
  },
  {
    immediate_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    SImode,
    0,
    1
  },
  {
    immediate_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "=&r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    immediate_operand,
    "n",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=&r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    HImode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=&r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    VOIDmode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    SImode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    VOIDmode,
    0,
    1
  },
  {
    register_operand,
    "=&r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    VOIDmode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    SImode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    VOIDmode,
    0,
    1
  },
  {
    const_int_operand,
    "n",
    VOIDmode,
    0,
    1
  },
  {
    register_operand,
    "+r",
    HImode,
    0,
    1
  },
  {
    immediate_operand,
    "n",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    bit_operand,
    "=Ur",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    immediate_operand,
    "n",
    HImode,
    0,
    1
  },
  {
    bit_operand,
    "0",
    HImode,
    0,
    1
  },
  {
    bit_operator,
    "",
    HImode,
    0,
    0
  },
  {
    bit_operand,
    "=Ur",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    immediate_operand,
    "n",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    immediate_operand,
    "n",
    HImode,
    0,
    1
  },
  {
    bit_operator,
    "",
    HImode,
    0,
    0
  },
  {
    register_operand,
    "=r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "=r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "0",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "r",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "",
    QImode,
    0,
    1
  },
  {
    general_operand_dst,
    "",
    QImode,
    0,
    1
  },
  {
    general_operand_src,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand_dst,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand_src,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand_dst,
    "",
    SImode,
    0,
    1
  },
  {
    general_operand_src,
    "",
    SImode,
    0,
    1
  },
  {
    general_operand_dst,
    "",
    SFmode,
    0,
    1
  },
  {
    general_operand_src,
    "",
    SFmode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    two_insn_adds_subs_operand,
    "",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "",
    SImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "",
    SImode,
    0,
    1
  },
  {
    two_insn_adds_subs_operand,
    "",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand,
    "",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    HImode,
    0,
    1
  },
  {
    bit_operand,
    "",
    QImode,
    0,
    1
  },
  {
    bit_operand,
    "",
    QImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "",
    VOIDmode,
    0,
    1
  },
  {
    0,
    "",
    VOIDmode,
    0,
    1
  },
  {
    jump_address_operand,
    "",
    VOIDmode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand_src,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "",
    QImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand,
    "",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "",
    SImode,
    0,
    1
  },
  {
    general_operand,
    "",
    SImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    QImode,
    0,
    1
  },
  {
    register_operand,
    "",
    SImode,
    0,
    1
  },
  {
    register_operand,
    "",
    SImode,
    0,
    1
  },
  {
    nonmemory_operand,
    "",
    QImode,
    0,
    1
  },
  {
    general_operand,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand,
    "",
    HImode,
    0,
    1
  },
  {
    register_operand,
    "",
    HImode,
    0,
    1
  },
  {
    bit_operand,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand,
    "",
    HImode,
    0,
    1
  },
  {
    general_operand,
    "",
    HImode,
    0,
    1
  },
};



const struct insn_data insn_data[] = 
{
  {
    "pushqi1_h8300",
    "mov.w\t%T0,@-r7",
    (insn_gen_fn) gen_pushqi1_h8300,
    &operand_data[1],
    1,
    0,
    1,
    1
  },
  {
    "pushqi1_h8300hs",
    "mov.l\t%S0,@-er7",
    (insn_gen_fn) gen_pushqi1_h8300hs,
    &operand_data[1],
    1,
    0,
    1,
    1
  },
  {
    "*h8300.md:147",
    (const PTR) output_2,
    0,
    &operand_data[2],
    2,
    0,
    6,
    2
  },
  {
    "*h8300.md:163",
    (const PTR) output_3,
    0,
    &operand_data[2],
    2,
    0,
    6,
    2
  },
  {
    "movstrictqi",
    (const PTR) output_4,
    (insn_gen_fn) gen_movstrictqi,
    &operand_data[4],
    2,
    0,
    4,
    2
  },
  {
    "pushhi1_h8300hs",
    "mov.l\t%S0,@-er7",
    (insn_gen_fn) gen_pushhi1_h8300hs,
    &operand_data[6],
    1,
    0,
    1,
    1
  },
  {
    "*h8300.md:237",
    (const PTR) output_6,
    0,
    &operand_data[7],
    2,
    0,
    6,
    2
  },
  {
    "*h8300.md:258",
    (const PTR) output_7,
    0,
    &operand_data[7],
    2,
    0,
    6,
    2
  },
  {
    "movstricthi",
    (const PTR) output_8,
    (insn_gen_fn) gen_movstricthi,
    &operand_data[9],
    2,
    0,
    4,
    2
  },
  {
    "movsi_h8300",
    (const PTR) output_9,
    (insn_gen_fn) gen_movsi_h8300,
    &operand_data[11],
    2,
    0,
    6,
    3
  },
  {
    "movsf_h8300",
    (const PTR) output_10,
    (insn_gen_fn) gen_movsf_h8300,
    &operand_data[13],
    2,
    0,
    6,
    3
  },
  {
    "movsi_h8300hs",
    (const PTR) output_11,
    (insn_gen_fn) gen_movsi_h8300hs,
    &operand_data[15],
    2,
    0,
    10,
    3
  },
  {
    "movsf_h8300h",
    (const PTR) output_12,
    (insn_gen_fn) gen_movsf_h8300h,
    &operand_data[17],
    2,
    0,
    6,
    2
  },
  {
    "*h8300.md:565",
    "btst	%Z1,%Y0",
    0,
    &operand_data[19],
    2,
    0,
    2,
    1
  },
  {
    "*h8300.md:574",
    "btst	%Z1,%Y0",
    0,
    &operand_data[21],
    2,
    0,
    1,
    1
  },
  {
    "*h8300.md:583",
    "btst	%Z1,%Y0",
    0,
    &operand_data[19],
    2,
    0,
    2,
    1
  },
  {
    "*h8300.md:592",
    "btst	%Z1,%Y0",
    0,
    &operand_data[23],
    2,
    0,
    1,
    1
  },
  {
    "tstqi",
    "mov.b	%X0,%X0",
    (insn_gen_fn) gen_tstqi,
    &operand_data[1],
    1,
    0,
    1,
    1
  },
  {
    "tsthi",
    "mov.w	%T0,%T0",
    (insn_gen_fn) gen_tsthi,
    &operand_data[6],
    1,
    0,
    1,
    1
  },
  {
    "tstsi",
    "mov.l	%S0,%S0",
    (insn_gen_fn) gen_tstsi,
    &operand_data[23],
    1,
    0,
    1,
    1
  },
  {
    "cmpqi",
    "cmp.b	%X1,%X0",
    (insn_gen_fn) gen_cmpqi,
    &operand_data[25],
    2,
    0,
    1,
    1
  },
  {
    "*h8300.md:645",
    "cmp.w	%T1,%T0",
    0,
    &operand_data[27],
    2,
    0,
    1,
    1
  },
  {
    "*h8300.md:654",
    "cmp.w	%T1,%T0",
    0,
    &operand_data[29],
    2,
    0,
    2,
    1
  },
  {
    "cmpsi",
    "cmp.l	%S1,%S0",
    (insn_gen_fn) gen_cmpsi,
    &operand_data[31],
    2,
    0,
    2,
    1
  },
  {
    "addqi3",
    "add.b	%X2,%X0",
    (insn_gen_fn) gen_addqi3,
    &operand_data[33],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:692",
    (const PTR) output_25,
    0,
    &operand_data[36],
    3,
    0,
    5,
    2
  },
  {
    "*h8300.md:706",
    (const PTR) output_26,
    0,
    &operand_data[39],
    3,
    0,
    4,
    2
  },
  {
    "addsi_h8300",
    (const PTR) output_27,
    (insn_gen_fn) gen_addsi_h8300,
    &operand_data[42],
    3,
    0,
    3,
    2
  },
  {
    "addsi_h8300h",
    (const PTR) output_28,
    (insn_gen_fn) gen_addsi_h8300h,
    &operand_data[45],
    3,
    0,
    4,
    2
  },
  {
    "subqi3",
    "sub.b	%X2,%X0",
    (insn_gen_fn) gen_subqi3,
    &operand_data[48],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:787",
    (const PTR) output_30,
    0,
    &operand_data[51],
    3,
    0,
    2,
    2
  },
  {
    "*h8300.md:798",
    (const PTR) output_31,
    0,
    &operand_data[51],
    3,
    0,
    2,
    2
  },
  {
    "subsi3_h8300",
    "sub.w	%f2,%f0\n\tsubx	%y2,%y0\n\tsubx	%z2,%z0",
    (insn_gen_fn) gen_subsi3_h8300,
    &operand_data[54],
    3,
    0,
    1,
    1
  },
  {
    "subsi3_h8300h",
    (const PTR) output_33,
    (insn_gen_fn) gen_subsi3_h8300h,
    &operand_data[57],
    3,
    0,
    2,
    2
  },
  {
    "mulqihi3",
    "mulxs.b	%X2,%T0",
    (insn_gen_fn) gen_mulqihi3,
    &operand_data[60],
    3,
    0,
    1,
    1
  },
  {
    "mulhisi3",
    "mulxs.w	%T2,%S0",
    (insn_gen_fn) gen_mulhisi3,
    &operand_data[63],
    3,
    0,
    1,
    1
  },
  {
    "umulqihi3",
    "mulxu	%X2,%T0",
    (insn_gen_fn) gen_umulqihi3,
    &operand_data[60],
    3,
    0,
    1,
    1
  },
  {
    "umulhisi3",
    "mulxu.w	%T2,%S0",
    (insn_gen_fn) gen_umulhisi3,
    &operand_data[63],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:885",
    "clrmac\n\tmac	@%2+,@%1+",
    0,
    &operand_data[66],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:897",
    "mac	@%2+,@%1+",
    0,
    &operand_data[66],
    4,
    0,
    1,
    1
  },
  {
    "udivmodqi4",
    (const PTR) output_40,
    (insn_gen_fn) gen_udivmodqi4,
    &operand_data[70],
    4,
    2,
    1,
    3
  },
  {
    "divmodqi4",
    (const PTR) output_41,
    (insn_gen_fn) gen_divmodqi4,
    &operand_data[70],
    4,
    2,
    1,
    3
  },
  {
    "udivmodhi4",
    (const PTR) output_42,
    (insn_gen_fn) gen_udivmodhi4,
    &operand_data[74],
    4,
    2,
    1,
    3
  },
  {
    "divmodhi4",
    (const PTR) output_43,
    (insn_gen_fn) gen_divmodhi4,
    &operand_data[74],
    4,
    2,
    1,
    3
  },
  {
    "*h8300.md:1006",
    (const PTR) output_44,
    0,
    &operand_data[78],
    3,
    0,
    2,
    2
  },
  {
    "*andorhi3",
    (const PTR) output_45,
    0,
    &operand_data[81],
    4,
    0,
    1,
    3
  },
  {
    "*h8300.md:1066",
    (const PTR) output_46,
    0,
    &operand_data[85],
    3,
    0,
    2,
    3
  },
  {
    "*h8300.md:1119",
    (const PTR) output_47,
    0,
    &operand_data[85],
    3,
    0,
    2,
    3
  },
  {
    "*h8300.md:1172",
    (const PTR) output_48,
    0,
    &operand_data[88],
    4,
    0,
    1,
    3
  },
  {
    "*h8300.md:1184",
    (const PTR) output_49,
    0,
    &operand_data[92],
    4,
    0,
    1,
    3
  },
  {
    "negqi2",
    "neg	%X0",
    (insn_gen_fn) gen_negqi2,
    &operand_data[48],
    2,
    0,
    1,
    1
  },
  {
    "neghi2_h8300h",
    "neg	%T0",
    (insn_gen_fn) gen_neghi2_h8300h,
    &operand_data[81],
    2,
    0,
    1,
    1
  },
  {
    "negsi2_h8300h",
    "neg	%S0",
    (insn_gen_fn) gen_negsi2_h8300h,
    &operand_data[54],
    2,
    0,
    1,
    1
  },
  {
    "one_cmplqi2",
    "not	%X0",
    (insn_gen_fn) gen_one_cmplqi2,
    &operand_data[48],
    2,
    0,
    1,
    1
  },
  {
    "*h8300.md:1286",
    "not	%s0\n\tnot	%t0",
    0,
    &operand_data[81],
    2,
    0,
    1,
    1
  },
  {
    "*h8300.md:1294",
    "not	%T0",
    0,
    &operand_data[81],
    2,
    0,
    1,
    1
  },
  {
    "*h8300.md:1308",
    "not	%w0\n\tnot	%x0\n\tnot	%y0\n\tnot	%z0",
    0,
    &operand_data[54],
    2,
    0,
    1,
    1
  },
  {
    "*h8300.md:1316",
    "not	%S0",
    0,
    &operand_data[54],
    2,
    0,
    1,
    1
  },
  {
    "branch_true",
    (const PTR) output_58,
    (insn_gen_fn) gen_branch_true,
    &operand_data[96],
    2,
    0,
    0,
    3
  },
  {
    "branch_false",
    (const PTR) output_59,
    (insn_gen_fn) gen_branch_false,
    &operand_data[96],
    2,
    0,
    0,
    3
  },
  {
    "jump",
    (const PTR) output_60,
    (insn_gen_fn) gen_jump,
    &operand_data[96],
    1,
    0,
    0,
    3
  },
  {
    "tablejump_h8300",
    "jmp	@%0",
    (insn_gen_fn) gen_tablejump_h8300,
    &operand_data[98],
    2,
    0,
    1,
    1
  },
  {
    "tablejump_h8300h",
    "jmp	@%0",
    (insn_gen_fn) gen_tablejump_h8300h,
    &operand_data[100],
    2,
    0,
    1,
    1
  },
  {
    "indirect_jump_h8300",
    "jmp	@%0",
    (insn_gen_fn) gen_indirect_jump_h8300,
    &operand_data[102],
    1,
    0,
    1,
    1
  },
  {
    "indirect_jump_h8300h",
    "jmp @%0",
    (insn_gen_fn) gen_indirect_jump_h8300h,
    &operand_data[103],
    1,
    0,
    1,
    1
  },
  {
    "call",
    (const PTR) output_65,
    (insn_gen_fn) gen_call,
    &operand_data[104],
    2,
    0,
    1,
    3
  },
  {
    "call_value",
    (const PTR) output_66,
    (insn_gen_fn) gen_call_value,
    &operand_data[106],
    3,
    0,
    1,
    3
  },
  {
    "nop",
    "nop",
    (insn_gen_fn) gen_nop,
    &operand_data[0],
    0,
    0,
    0,
    1
  },
  {
    "*h8300.md:1604",
    (const PTR) output_68,
    0,
    &operand_data[109],
    2,
    0,
    2,
    2
  },
  {
    "*h8300.md:1614",
    (const PTR) output_69,
    0,
    &operand_data[109],
    2,
    0,
    2,
    2
  },
  {
    "zero_extendqisi2",
    (const PTR) output_70,
    (insn_gen_fn) gen_zero_extendqisi2,
    &operand_data[111],
    2,
    0,
    2,
    2
  },
  {
    "*h8300.md:1643",
    (const PTR) output_71,
    0,
    &operand_data[113],
    2,
    0,
    3,
    2
  },
  {
    "*h8300.md:1654",
    "extu.l	%S0",
    0,
    &operand_data[115],
    2,
    0,
    1,
    1
  },
  {
    "*h8300.md:1668",
    (const PTR) output_73,
    0,
    &operand_data[109],
    2,
    0,
    2,
    2
  },
  {
    "*h8300.md:1678",
    "exts.w	%T0",
    0,
    &operand_data[117],
    2,
    0,
    1,
    1
  },
  {
    "extendqisi2",
    (const PTR) output_75,
    (insn_gen_fn) gen_extendqisi2,
    &operand_data[111],
    2,
    0,
    2,
    2
  },
  {
    "*h8300.md:1704",
    (const PTR) output_76,
    0,
    &operand_data[119],
    2,
    0,
    2,
    2
  },
  {
    "*h8300.md:1714",
    "exts.l	%S0",
    0,
    &operand_data[115],
    2,
    0,
    1,
    1
  },
  {
    "*h8300.md:1764",
    (const PTR) output_78,
    0,
    &operand_data[121],
    5,
    0,
    2,
    3
  },
  {
    "*h8300.md:1799",
    (const PTR) output_79,
    0,
    &operand_data[126],
    5,
    0,
    2,
    3
  },
  {
    "*h8300.md:1834",
    (const PTR) output_80,
    0,
    &operand_data[131],
    5,
    0,
    2,
    3
  },
  {
    "*rotlqi3_1",
    (const PTR) output_81,
    0,
    &operand_data[136],
    3,
    0,
    1,
    3
  },
  {
    "*rotlhi3_1",
    (const PTR) output_82,
    0,
    &operand_data[139],
    3,
    0,
    1,
    3
  },
  {
    "*rotlsi3_1",
    (const PTR) output_83,
    0,
    &operand_data[142],
    3,
    0,
    1,
    3
  },
  {
    "*h8300.md:1915",
    "sub.w	%0,%0\n\tbld	%Z2,%Y1\n\tbst	#0,%X0",
    0,
    &operand_data[145],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:1929",
    "sub.w	%0,%0\n\tbild	%Z2,%Y1\n\tbst	#0,%X0",
    0,
    &operand_data[148],
    4,
    0,
    1,
    1
  },
  {
    "*h8300.md:1945",
    (const PTR) output_86,
    0,
    &operand_data[152],
    3,
    0,
    1,
    3
  },
  {
    "*h8300.md:1956",
    (const PTR) output_87,
    0,
    &operand_data[155],
    3,
    0,
    1,
    3
  },
  {
    "*h8300.md:1971",
    (const PTR) output_88,
    0,
    &operand_data[158],
    4,
    0,
    1,
    3
  },
  {
    "*h8300.md:1984",
    (const PTR) output_89,
    0,
    &operand_data[162],
    4,
    0,
    1,
    3
  },
  {
    "*h8300.md:2015",
    "bld	#0,%R2\n\tbst	%Z1,%Y0 ; i1",
    0,
    &operand_data[166],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:2044",
    "bld	%Z2,%Y1\n\t%b4	#0,%R0\n\tbst	#0,%R0; bl1",
    0,
    &operand_data[169],
    5,
    0,
    1,
    1
  },
  {
    "*h8300.md:2057",
    "bld	%Z2,%Y1\n\t%b5	%Z4,%Y3\n\tbst	#0,%R0; bl3",
    0,
    &operand_data[174],
    6,
    0,
    1,
    1
  },
  {
    "*h8300.md:2076",
    "or\t%X1,%s0",
    0,
    &operand_data[180],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:2087",
    "or.w\t%T1,%f0",
    0,
    &operand_data[183],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:2099",
    "or\t%X1,%s0",
    0,
    &operand_data[186],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:2110",
    "xor\t%X1,%s0",
    0,
    &operand_data[180],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:2121",
    "xor.w\t%T1,%f0",
    0,
    &operand_data[183],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:2133",
    "xor\t%X1,%s0",
    0,
    &operand_data[186],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:2144",
    "mov.b\t%s2,%t0",
    0,
    &operand_data[189],
    3,
    0,
    1,
    1
  },
  {
    "*h8300.md:2156",
    "mov.w\t%f2,%e0",
    0,
    &operand_data[192],
    3,
    0,
    1,
    1
  },
  {
    "pushqi1",
    0,
    (insn_gen_fn) gen_pushqi1,
    &operand_data[195],
    1,
    0,
    0,
    0
  },
  {
    "movqi",
    0,
    (insn_gen_fn) gen_movqi,
    &operand_data[196],
    2,
    0,
    0,
    0
  },
  {
    "pushhi1_h8300",
    0,
    (insn_gen_fn) gen_pushhi1_h8300,
    &operand_data[198],
    1,
    0,
    0,
    0
  },
  {
    "pushhi1",
    0,
    (insn_gen_fn) gen_pushhi1,
    &operand_data[198],
    1,
    0,
    0,
    0
  },
  {
    "movhi",
    0,
    (insn_gen_fn) gen_movhi,
    &operand_data[199],
    2,
    0,
    0,
    0
  },
  {
    "movsi",
    0,
    (insn_gen_fn) gen_movsi,
    &operand_data[201],
    2,
    0,
    0,
    0
  },
  {
    "movsf",
    0,
    (insn_gen_fn) gen_movsf,
    &operand_data[203],
    2,
    0,
    0,
    0
  },
  {
    "cmphi",
    0,
    (insn_gen_fn) gen_cmphi,
    &operand_data[205],
    2,
    0,
    0,
    0
  },
  {
    "addhi3",
    0,
    (insn_gen_fn) gen_addhi3,
    &operand_data[207],
    3,
    0,
    0,
    0
  },
  {
    "addhi3+1",
    0,
    0,
    &operand_data[210],
    2,
    0,
    0,
    0
  },
  {
    "addsi3",
    0,
    (insn_gen_fn) gen_addsi3,
    &operand_data[212],
    3,
    0,
    0,
    0
  },
  {
    "addsi3+1",
    0,
    0,
    &operand_data[215],
    2,
    0,
    0,
    0
  },
  {
    "subhi3",
    0,
    (insn_gen_fn) gen_subhi3,
    &operand_data[217],
    3,
    0,
    0,
    0
  },
  {
    "subsi3",
    0,
    (insn_gen_fn) gen_subsi3,
    &operand_data[212],
    3,
    0,
    0,
    0
  },
  {
    "andqi3",
    0,
    (insn_gen_fn) gen_andqi3,
    &operand_data[220],
    3,
    0,
    0,
    0
  },
  {
    "andhi3",
    0,
    (insn_gen_fn) gen_andhi3,
    &operand_data[207],
    3,
    0,
    0,
    0
  },
  {
    "andsi3",
    0,
    (insn_gen_fn) gen_andsi3,
    &operand_data[212],
    3,
    0,
    0,
    0
  },
  {
    "iorqi3",
    0,
    (insn_gen_fn) gen_iorqi3,
    &operand_data[220],
    3,
    0,
    0,
    0
  },
  {
    "iorhi3",
    0,
    (insn_gen_fn) gen_iorhi3,
    &operand_data[207],
    3,
    0,
    0,
    0
  },
  {
    "iorsi3",
    0,
    (insn_gen_fn) gen_iorsi3,
    &operand_data[212],
    3,
    0,
    0,
    0
  },
  {
    "xorqi3",
    0,
    (insn_gen_fn) gen_xorqi3,
    &operand_data[220],
    3,
    0,
    0,
    0
  },
  {
    "xorhi3",
    0,
    (insn_gen_fn) gen_xorhi3,
    &operand_data[207],
    3,
    0,
    0,
    0
  },
  {
    "xorsi3",
    0,
    (insn_gen_fn) gen_xorsi3,
    &operand_data[212],
    3,
    0,
    0,
    0
  },
  {
    "neghi2",
    0,
    (insn_gen_fn) gen_neghi2,
    &operand_data[207],
    2,
    0,
    0,
    0
  },
  {
    "neghi2_h8300",
    0,
    (insn_gen_fn) gen_neghi2_h8300,
    &operand_data[207],
    2,
    4,
    0,
    0
  },
  {
    "negsi2",
    0,
    (insn_gen_fn) gen_negsi2,
    &operand_data[212],
    2,
    0,
    0,
    0
  },
  {
    "negsi2_h8300",
    0,
    (insn_gen_fn) gen_negsi2_h8300,
    &operand_data[212],
    2,
    4,
    0,
    0
  },
  {
    "one_cmplhi2",
    0,
    (insn_gen_fn) gen_one_cmplhi2,
    &operand_data[81],
    2,
    0,
    1,
    0
  },
  {
    "one_cmplsi2",
    0,
    (insn_gen_fn) gen_one_cmplsi2,
    &operand_data[54],
    2,
    0,
    1,
    0
  },
  {
    "ble",
    0,
    (insn_gen_fn) gen_ble,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "bleu",
    0,
    (insn_gen_fn) gen_bleu,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "bge",
    0,
    (insn_gen_fn) gen_bge,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "bgeu",
    0,
    (insn_gen_fn) gen_bgeu,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "blt",
    0,
    (insn_gen_fn) gen_blt,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "bltu",
    0,
    (insn_gen_fn) gen_bltu,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "bgt",
    0,
    (insn_gen_fn) gen_bgt,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "bgtu",
    0,
    (insn_gen_fn) gen_bgtu,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "beq",
    0,
    (insn_gen_fn) gen_beq,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "bne",
    0,
    (insn_gen_fn) gen_bne,
    &operand_data[96],
    1,
    0,
    0,
    0
  },
  {
    "tablejump",
    0,
    (insn_gen_fn) gen_tablejump,
    &operand_data[223],
    2,
    0,
    0,
    0
  },
  {
    "indirect_jump",
    0,
    (insn_gen_fn) gen_indirect_jump,
    &operand_data[225],
    1,
    0,
    0,
    0
  },
  {
    "zero_extendqihi2",
    0,
    (insn_gen_fn) gen_zero_extendqihi2,
    &operand_data[226],
    2,
    0,
    0,
    0
  },
  {
    "zero_extendhisi2",
    0,
    (insn_gen_fn) gen_zero_extendhisi2,
    &operand_data[228],
    2,
    0,
    0,
    0
  },
  {
    "extendqihi2",
    0,
    (insn_gen_fn) gen_extendqihi2,
    &operand_data[229],
    2,
    0,
    0,
    0
  },
  {
    "extendhisi2",
    0,
    (insn_gen_fn) gen_extendhisi2,
    &operand_data[228],
    2,
    0,
    0,
    0
  },
  {
    "ashlqi3",
    0,
    (insn_gen_fn) gen_ashlqi3,
    &operand_data[230],
    3,
    0,
    0,
    0
  },
  {
    "ashrqi3",
    0,
    (insn_gen_fn) gen_ashrqi3,
    &operand_data[230],
    3,
    0,
    0,
    0
  },
  {
    "lshrqi3",
    0,
    (insn_gen_fn) gen_lshrqi3,
    &operand_data[230],
    3,
    0,
    0,
    0
  },
  {
    "ashlhi3",
    0,
    (insn_gen_fn) gen_ashlhi3,
    &operand_data[233],
    3,
    0,
    0,
    0
  },
  {
    "lshrhi3",
    0,
    (insn_gen_fn) gen_lshrhi3,
    &operand_data[236],
    3,
    0,
    0,
    0
  },
  {
    "ashrhi3",
    0,
    (insn_gen_fn) gen_ashrhi3,
    &operand_data[239],
    3,
    0,
    0,
    0
  },
  {
    "ashlsi3",
    0,
    (insn_gen_fn) gen_ashlsi3,
    &operand_data[242],
    3,
    0,
    0,
    0
  },
  {
    "lshrsi3",
    0,
    (insn_gen_fn) gen_lshrsi3,
    &operand_data[242],
    3,
    0,
    0,
    0
  },
  {
    "ashrsi3",
    0,
    (insn_gen_fn) gen_ashrsi3,
    &operand_data[242],
    3,
    0,
    0,
    0
  },
  {
    "rotlqi3",
    0,
    (insn_gen_fn) gen_rotlqi3,
    &operand_data[230],
    3,
    0,
    0,
    0
  },
  {
    "rotlhi3",
    0,
    (insn_gen_fn) gen_rotlhi3,
    &operand_data[239],
    3,
    0,
    0,
    0
  },
  {
    "rotlsi3",
    0,
    (insn_gen_fn) gen_rotlsi3,
    &operand_data[245],
    3,
    0,
    0,
    0
  },
  {
    "insv",
    0,
    (insn_gen_fn) gen_insv,
    &operand_data[248],
    4,
    0,
    0,
    0
  },
  {
    "extzv",
    0,
    (insn_gen_fn) gen_extzv,
    &operand_data[252],
    4,
    0,
    0,
    0
  },
};


const char *
get_insn_name (code)
     int code;
{
  return insn_data[code].name;
}
